TSMC Shifts CoW Packaging Work to Third-Party Contractors as AI Demand Strains Capacity

KEY TAKEAWAYS

·TSMC is outsourcing the chip-on-wafer stage of CoWoS advanced packaging to third-party OSAT providers to address capacity constraints driven by AI chip demand.
·CoWoS lead times exceeded six months in late 2025, prompting TSMC to distribute production beyond its internal fabs despite historically tight control over the process.
·Taiwan's OSAT sector, led by ASE Technology, is expected to capture the bulk of outsourced CoW work, with capital expenditure in advanced packaging projected above USD 1 billion this year.

Outsourcing the Bottleneck

Taiwan Semiconductor Manufacturing Co. is moving portions of its chip-on-wafer production to outsourced semiconductor assembly and test providers, according to semiconductor industry sources. The shift marks a strategic response to capacity limitations in one of the most critical stages of advanced packaging for artificial intelligence processors.

CoWoS, short for chip-on-wafer-on-substrate, has become a linchpin technology for high-performance computing and AI accelerators. The packaging method stacks multiple chips vertically and integrates them with high-bandwidth memory, enabling the data throughput required by large language models and neural network training workloads. TSMC pioneered the technology and has maintained tight control over the process, making this outsourcing decision a notable departure.

The chip-on-wafer stage involves mounting individual chiplets onto a silicon interposer before the entire assembly is bonded to a substrate. It requires precision alignment and thermal management capabilities that few facilities possess. By distributing this work to specialized OSAT partners, TSMC can increase throughput without waiting for internal fab expansions to come online.

Capacity Crunch in the AI Era

Demand for CoWoS packaging has surged alongside the AI boom. Nvidia, AMD, and a growing roster of custom silicon designers rely on TSMC's advanced packaging to deliver the multi-die configurations that underpin their flagship products. Nvidia's H100 and H200 accelerators, for instance, depend on CoWoS to integrate GPU dies with HBM3 memory stacks, a configuration that has become standard in hyperscale data centers from Singapore to Seoul.

TSMC has been racing to expand its CoWoS capacity. The company announced plans earlier this year to triple production by the end of 2026, investing in new cleanroom space at its竹南 and 中科 facilities. Yet the ramp has struggled to keep pace with order books. Lead times for CoWoS packaging stretched beyond six months in late 2025, forcing some chip designers to delay product launches or secure allocations years in advance.

Outsourcing the CoW stage offers a faster path to relief. OSAT providers such as ASE Technology, Amkor Technology, and JCET have been building out advanced packaging lines of their own, often with encouragement and technical guidance from TSMC. These firms bring mature process control and economies of scale in assembly operations, even if they lack TSMC's leading-edge wafer fabrication expertise.

Regional Implications

The move has ripple effects across Asia's semiconductor ecosystem. Taiwan's OSAT sector stands to benefit most directly, with ASE Technology already operating fan-out wafer-level packaging lines that share process similarities with CoW assembly. The company's Kaohsiung facility has been earmarked for capacity additions, and industry analysts expect capital expenditure in advanced packaging to climb above USD 1 billion across Taiwan's OSAT players this year.

South Korea's packaging houses are also positioning for a share of the work. Samsung Electronics has its own advanced packaging roadmap, but independent OSATs like Signetics and Hana Micron have been courting TSMC and its customers. Japan's Ibiden and Shinko Electric, dominant substrate suppliers, may see order momentum as CoWoS volumes rise, though the CoW stage itself remains outside their core competence.

For China's semiconductor industry, the outsourcing shift presents a more complex picture. JCET, headquartered in Jiangyin, has technical capabilities in flip-chip and wafer-level packaging, but U.S. export controls on advanced packaging equipment and EDA tools have constrained its ability to serve leading-edge AI applications. TSMC's outsourcing is unlikely to route significant CoW volume to mainland China in the near term, given both regulatory and customer preference dynamics.

What Comes Next

TSMC's decision to outsource CoW work is unlikely to be a one-time adjustment. The company has historically kept its most advanced processes in-house, viewing them as competitive moats. The fact that it is now willing to share CoW production suggests that demand is outrunning even aggressive internal expansion plans.

The next constraint may shift downstream. Even with more CoW capacity, the substrate supply chain remains tight. Organic substrates capable of handling the thermal and electrical loads of multi-chiplet AI processors require specialized materials and long lead times. Substrate makers in Japan and Taiwan are ramping production, but shortages could re-emerge if AI chip demand continues its current trajectory.

TSMC has not disclosed which OSAT partners will receive CoW outsourcing contracts, nor has it specified volume targets. The company is expected to provide updates during its quarterly earnings briefings, where advanced packaging has become a recurring topic. For now, the move signals that Asia's semiconductor leaders are adapting infrastructure as quickly as capital and physics allow, even if it means loosening their grip on proprietary processes.

Asia's overnight moves, distilled into a five-minute read.

Outsourcing the Bottleneck

Capacity Crunch in the AI Era

Regional Implications

What Comes Next

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