JCET Eyes $968 Million to Scale AI Packaging Lines

Capital Push into Advanced Packaging

JCET Group announced plans to raise CNY 6.5 billion - approximately $968 million - through a private share placement targeting expansion across advanced packaging and testing operations. The investment will finance capacity buildouts in high-performance computing, power modules, wafer-level packaging, and memory applications, according to the company.

The move positions China's largest outsourced semiconductor assembly and test (OSAT) provider to capture a larger share of AI infrastructure demand while deepening its role in the domestic supply chain. JCET currently operates facilities in Jiangyin, Chengdu, and Wuxi, alongside overseas plants acquired through its 2015 purchase of Singapore's STATS ChipPAC.

HPC and Memory at the Core

High-performance computing packaging has become the fastest-growing segment in the OSAT market, driven by demand for chiplet architectures, 2.5D and 3D stacking, and thermal management solutions required by AI accelerators and data-center processors. JCET's expansion plan places HPC at the center of its capital allocation, a signal that it expects sustained orders from Chinese GPU designers, server CPU developers, and hyperscale operators building out domestic cloud infrastructure.

The memory packaging component of the investment targets high-bandwidth memory (HBM) and DDR5 modules, both critical to AI training clusters and inference workloads. JCET has been qualifying HBM packaging processes since late 2024, aiming to compete with South Korean and Taiwanese rivals that currently dominate the segment.

Power module packaging, meanwhile, serves the automotive and industrial electronics markets, where China has built scale in electric vehicle components and renewable energy inverters. Wafer-level packaging rounds out the portfolio, addressing mobile and IoT applications that demand smaller form factors and lower power envelopes.

Strategic Timing Amid Export Controls

The capital raise comes as China accelerates investment in semiconductor self-sufficiency. Export controls introduced by the United States in 2023 and 2024 have restricted access to leading-edge lithography tools and certain chip architectures, pushing Chinese chipmakers and their suppliers to invest heavily in mature-node capacity and alternative packaging technologies that can close performance gaps without relying on sub-3nm process nodes.

Advanced packaging - particularly chiplet integration and heterogeneous assembly - offers a pathway to boost system-level performance by combining multiple dies with different functions and process nodes in a single package. JCET's expansion aligns with this national strategy, providing domestic fabless companies and integrated device manufacturers with an alternative to Taiwan Semiconductor Manufacturing Company's advanced packaging services and to South Korean OSATs.

Competitive Landscape

JCET competes globally with ASE Technology Holding, Amkor Technology, and Powertech Technology, all of which have announced capacity expansions in advanced packaging over the past eighteen months. ASE, the world's largest OSAT, disclosed plans in early 2025 to add $1.2 billion in 2.5D and fan-out wafer-level packaging capacity across Taiwan and Malaysia. Amkor is building a $2 billion facility in Arizona under the U.S. CHIPS Act, targeting American and European customers.

Within China, JCET faces growing competition from Tongfu Microelectronics and Tianshui Huatian Technology, both of which have received government-backed investment to expand HPC and automotive packaging lines. The domestic OSAT market is consolidating around a handful of players capable of meeting the technical and capital requirements of advanced nodes.

Funding Structure and Execution Risk

Private placements in China's A-share market typically involve strategic investors, state-backed funds, and institutional buyers. JCET has not yet disclosed the investor roster or the timeline for closing the placement, though regulatory filings are expected within the next quarter. The company will need approval from the China Securities Regulatory Commission before proceeding.

Execution risk centers on yield ramp and customer qualification. Advanced packaging processes, especially HBM stacking and chiplet interconnects, require tight tolerances and sophisticated thermal and electrical testing. JCET's ability to ramp production while maintaining competitive yields will determine whether the investment translates into market-share gains or margin pressure.

What Comes Next

The expansion is scheduled to begin in the fourth quarter of this year, with initial production lines expected online by mid-2027. JCET will likely prioritize HPC capacity first, given the higher margins and strategic importance of AI infrastructure projects. Memory packaging capacity will follow, contingent on customer commitments from Chinese DRAM and NAND suppliers.

Industry observers will watch whether JCET can secure long-term supply agreements with leading Chinese chip designers, including those developing AI accelerators and automotive processors. Such agreements would de-risk the capital deployment and signal confidence in the domestic ecosystem's ability to compete with established players in Taiwan, South Korea, and the United States.